The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating a write strobe signal activated in a write operation and transferring data from an external device to an internal data line using the generated write strobe signal.
In general, a semiconductor memory device such as Double Data Rate Synchronous DRAM (DDR SDRAM) includes more than ten million memory cells for storing data. Such a semiconductor memory device stores data or outputs the data according to a command requested by the central processing unit (CPU). That is, when the CPU requests a write operation, the semiconductor memory device stores data in a memory cell corresponding to an address inputted from the CPU. When the CPU requests a read operation, the semiconductor memory device reads data stored in a memory cell corresponding to an address inputted from the CPU. In other word, data inputted through an input/output pad is inputted to a memory cell through a data input path in a write operation. In a read operation, data stored in a memory cell is read through a data output path and outputted through the input/output pad.
FIG. 1 is a block diagram illustrating a partial structure of a semiconductor memory device according to prior art.
Referring to FIG. 1, the semiconductor memory device according to prior art includes a data aligner 110, a write pulse generator 130, a delay 150, and a data transfer unit 170.
The data aligner 110 aligns serial input data R0, F0, R1, F1, R2, F2, R3, and F3 (see FIG. 2) that are sequentially inputted through the input/output pad DQ in response to a data strobe signal DQS and outputs the aligned serial input data as 0th to 7th parallel output data OUT<0:7>. That is, the data aligner 110 latches the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 by synchronizing the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 with a falling edge and a rising edge of a data strobe signal DQS. The latched serial input data R0, F0, R1, F1, R2, F2, R3, and F3 become the 0th to 7th parallel output data OUT<0:7>. Here, the burst length BL is 8 because the number of the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 is eight.
The write pulse generator 130 generates a write pulse signal WTP in response to a write command WT, a CAS latency CL, an additive latency AL, and a burst length BL. The write pulse signal WTP has a predetermined pulse width.
The delay unit 150 generates a write strobe signal DCLKP by reflecting an asynchronous delay time to the write pulse signal. Here, the generated write strobe signal DCLKP is delayed until the data aligner 110 completely aligns the serial input data R0, F0, R1, F1, R2, F2, R3, and F3. That is, the write strobe signal DCLKP is activated at a time of completely aligning all of the serial input data R0, F0, R1, F1, R2, F2, R3, and F3. Here, the write strobe signal DCLKP has a pulse width identical to the write pulse signal WTP.
The data transfer unit 170 transfers 0th to 7th output data OUT<0:7> of the data aligner 110 to 0th to 7th global input/output lines GIO<0:7> in response to the write strobe signal DCLKP.
FIG. 2 is a diagram for describing signals related to a semiconductor memory device of FIG. 1.
Referring to FIGS. 1 and 2, when a write command WT is applied after being synchronized with an external clock signal CLK, a data strobe signal DQS and serial input data R0, F0, R1, F1, R2, F2, R3, and F3 are inputted corresponding to CAS latency CL and additive latency AL. The data aligner 110 latches the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 in response to the data strobe signal DQS. The latched serial input data R0, F0, R1, F1, R2, F2, R3, and F3 becomes the 0th to 7th parallel output data OUT<0:7>.
The write strobe signal DCLKP is activated when the data aligner 110 completely aligns the serial input data R0, F0, R1, F1, R2, F2, R3, and F3. By delaying such a write strobe signal DCLKP using the delay 150 (see FIG. 1), it is possible to activate the write strobe signal DCLKP when the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 are completely aligned because the write pulse signal WTP (not shown in FIG. 2) is activated at last input data F3 corresponding to CAS latency CL, additive latency AL and burst latency BL. Each of the 0th to 7th parallel output data OUT<0:7> is transferred to corresponding 0th to 7th global input/output lines GIO<0:7> in response to the write strobe signal DCLKP.
Hereinafter, the write strobe signal DCLKP will be described in more detail. The write strobe signal DCLKP is activated when the serial input data R0, F0, R1, F1, R2, F2, R3, and F3 are completely aligned. Also, the write strobe signal DCLKP is inactivated after passing a time that allows the 0th to 7th output data OUT<0:7> to be transferred to corresponding global input/output lines GIO<0:7>. That is, a time of activating and a time of inactivating the write strobe signal DCLKP are defined by the write pulse signal WTP and the delay 150 that delays the write pulse signal.
Meanwhile, semiconductor memory devices have been advanced to perform operation in a high speed. Accordingly, an operation frequency of semiconductor memory devices has increased and semiconductor memory devices are being designed to perform consecutive write operations. However, such an operation of the semiconductor memory devices also causes other problem.
FIGS. 3A and 3B are diagrams describing a normal operation and abnormal operation of a semiconductor memory device according to prior art. That is, FIGS. 3A and 3B show an operation of a semiconductor memory device when a write command is continuously inputted thereto. For the sake of easier description, a write command inputted first is referred as a first write command WT1, and a write command inputted second is referred as a second write command WT2.
At first, the normal operation of the semiconductor memory device will be described with reference to FIGS. 1 and 3A. FIG. 3A shows an operation of a semiconductor memory device having a comparatively low operation frequency.
When the first write command WT1 is applied, the data strobe signal DQS is activated, and the serial input data AR0, AF0, AR1, AF1, AR2, AF2, AR3, and AF3 corresponding to the first write command WT1 are sequentially inputted. Then, the serial input data AR0, AF0, AR1, AF1, AR2, AF2, AR3, and AF3 are aligned by the data aligner 110 and become 0th to 7th output data OUT<0:7>. For the sake of easier description, FIG. 3A shows the 0th output data OUT<0> and a corresponding 0th global input/output line GIO<0>. That is, the 0th output data OUT<0> outputs AR0, AR1, AR2, and AR3 corresponding to the first write command WT1.
The write strobe signal DCLKP generated by the delay 150 is activated at the center of the last input data AR3 corresponding to the write command WT1 and inactivated after passing a predetermined time Δt. Here, the predetermined time Δt corresponds to a pulse width of a write pulse signal WTP generated by the write pulse generator 130. Since a pulse width is included in the last input data AR3 corresponding to the first write command WT1 in case of a semiconductor memory device having a comparative low operation frequency, the last input data AR3 is safely received through the 0th global input/output line GIO<0>.
When the second write command WT2 is applied, serial input data BR0, BF0, BR1, BF1, BR2, BF2, BR3, and BF3 corresponding the second write command WT2 are sequentially applied after the last input data AR3 corresponding to the first write command WT1. Similarly, the serial input data BR0, BF0, BR1, BF1, BR2, BF2, BR3, and BF3 are aligned in the data aligner 110 and become 0th to 7th output data OUT<0:7>. Then, the write strobe signal DCLKP is activated at the center of the last input data BR3 corresponding to the second write command WT2 and is inactivated after passing a predetermined time Δt. Therefore, the last input data BR3 corresponding to the second write command WT2 is safely received through the 0th global input/output line GIO<0>.
Hereinafter, an abnormal operation of a semiconductor memory device will be described with reference to FIGS. 1 and 3B. FIG. 3B shows operation of a semiconductor memory device having a comparatively high operation frequency.
When a first write command WT1 is applied, a data strobe signal DQS is activated and serial input data AR0, AF0, AR1, AF1, AR2, AF2, AR3, and AF3 corresponding to the first write command WT1 are sequentially inputted. Then, the serial input data AR0, AF0, AR1, AF1, AR2, AF2, AR3, and AF3 are aligned by the data aligner 110 and become 0th to 7th output data OUT<0:7>. FIG. 3B exemplarily shows only 0th output data OUT<0> among the 0th to 7th output data OUT<0:7> and a 0th global input/output line GIO<0>.
Then, a write strobe signal DCLKP generated from the delay 150 is activated at the center of the last input data AR3 corresponding to the first write command WT1 and is inactivated after passing a predetermined time Δt. In case of a semiconductor memory device having a comparatively high operation frequency, frequencies of an applied external clock signal CLK and a data strobe signal DQS are also high and the data aligner 110 operates according to the high frequency thereof. Therefore, a valid data period of each of the 0th to 7th output data OUT<0:7> becomes shortened. The shortened valid data period means that the write strobe signal DCLKP activated for a predetermined time Δt may influence input data after the predetermined time Δt.
That is, the write strobe signal DCLKP activated at the center of the last input data AR3 corresponding to the first write command WT1 is inactivated after passing a predetermined time Δt. However, the first input data BR0 corresponding to the second write command WT2 is outputted as the 0th output data OUT<0> before the write strobe signal DCLKP is inactivated as the operation frequency increases. Therefore, the first input data BR0 corresponding to the second write command WT2 is transferred to the 0th global input/output line GIO<0>. That is, the semiconductor memory device performs an abnormal operation.
As described above, the semiconductor memory device according to the prior art may not transfer data to a corresponding global input/output line because the last input data AR3 corresponding to the first write command WT1 and the first input data BR0 corresponding to the second write command WT2 are included in the activation period of the same write strobe signal DCLKP. Therefore, the reliability of the semiconductor memory device according to prior art is deteriorated in the write operation.